Modern wireless devices, such as mobile communication devices, combine digital, analog, and radio frequency circuits together in close proximity. Over time, these systems have become more integrated, and packaged into smaller volumes. They have also been designed to perform more functions, and are now approaching the processing power of so called “palm top” computing platforms. These devices are now typically used, for example, to browse content on the Internet, execute software applications, and communicate in a variety of modes.
As digital systems have become increasingly faster, requiring higher frequency clock sources, designers have had to deal with the harmonic content of these clocks since they can be radiated and conducted to other circuitry in the device, causing performance degradation, if not worse. A typical way to deal with the problem is to select clock frequencies such that their harmonics do not fall within bands used by the radio frequency circuits, and specifically the receive bands in which the device receives RF signals.
The problem is made much more difficult, however, when a high frequency clock signal is switched on and off, such as may be done to reduce power consumption. Switching the high frequency clock signal on and off periodically results in an amplitude modulated signal. The harmonic content of such a signal tends to be broadband, with spurs around the harmonics of the high frequency clock signal located plus and minus the switching frequency of the modulating signal. These spurs and their harmonics make it nearly impossible to remove the resulting noise from the receive band by conventional frequency planning. Therefore there is a need for a means by which such broadband harmonic content can be reduced at the radio frequency components of the device.